By Zhuo Ma, Zhenyu Zhao, Yang Guo, Lunguo Xie, Jinshan Yu (auth.), Weixia Xu, Liquan Xiao, Pingjing Lu, Jinwen Li, Chengyi Zhang (eds.)
This booklet constitutes the refereed complaints of the sixteenth nationwide convention on machine Engineering and expertise, NCCET 2012, held in Shanghai, China, in August 2012. The 27 papers offered have been rigorously reviewed and chosen from 108 submissions. they're geared up in topical sections named: microprocessor and implementation; layout of integration circuit; I/O interconnect; and dimension, verification, and others.
Read Online or Download Computer Engineering and Technology: 16th National Conference, NCCET 2012, Shanghai, China, August 17-19, 2012, Revised Selected Papers PDF
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Additional info for Computer Engineering and Technology: 16th National Conference, NCCET 2012, Shanghai, China, August 17-19, 2012, Revised Selected Papers
In recent years, many stream architectures aiming at stream application have been proposed [1-6], and they have obvious advantages in domains of signal processing, multimedia and scientific computing. The main idea of stream processing is organizing the stream to data streams and computation kernels, utilizing the locality and parallelism of the application to conceal memory access latency. The key of stream architecture is to provide powerful computing ability and hide the memory access latency at the same time.
The hardware status and results will be printed to the server screen and the log files. Once the real-time errors in hardware design are detected by the checkers, the simulator will pause and invoke a debug interface to check the errors. If the test case exits from the bad address or if the hardware status is inconsistent, MGTE platform will report the sequence of the error instructions from the logs or the address sequence of the inconsistentdata for troubleshooting. 2 X. Yan et al. MGTE Hardware Environment MGTE hardware environment refers to the PX-16 processor full-chip design codes and simulation related codes, including the global flow control module, processor model, memory model, Flash model, the IO reference design model, global initialization module and global checkers and global monitors, as shown in Fig.
2 (2) Establishing the Scale Space Similar to the SIFT, SURF presents image scale space using image pyramid. In a certain sample step, a series of boxes with different sizes are used to calculate DoH(Determinant of Hessian) at each sample point, which generates the first octave of scale space; then the sample step is increased, and a series of boxes with different size are used to calculate DoH at each sample point, which generates the second octave of scale space. In a similar way, the third and the fourth octave of scale space 30 Z.