Manufacturing Challenges in Electronic Packaging by Y.C. Lee, W.T. Chen

By Y.C. Lee, W.T. Chen

About 5 to 6 years in the past, the phrases 'packaging and production' began to be used jointly to stress that we have got to make not just a couple of yet millions or maybe hundreds of thousands of programs which meet practical specifications. the purpose of this ebook is to supply the a lot wanted studies and in-depth discussions at the complex issues surrounding packaging and production. the 1st bankruptcy offers a accomplished evaluate of producing chal­ lenges in digital packaging in response to traits estimated by means of diversified assets. just about all the practical necessities have already been met by way of applied sciences verified in laboratories. even if, it will take large efforts to enforce those applied sciences for mass construction or versatile production. the themes the most important to this implementation are mentioned within the following chapters: bankruptcy 2: demanding situations in solder meeting applied sciences; bankruptcy three: checking out and characterization; bankruptcy four: layout for manufacture and meeting of digital applications; bankruptcy five: strategy modeling, optimization and keep watch over in electronics production; and bankruptcy 6: built-in production approach for revealed circuit board meeting. The electronics-based items are very aggressive and changing into progressively more application-specific. Their applications may still satisfy expense, velocity, energy, weight, measurement, reliability and time-to-market specifications. extra importantly, the programs might be manufacturable in mass or versatile creation traces. those chapters are very good references for pros who have to meet the problem via layout and production advancements. This publication also will introduce scholars to the severe concerns for aggressive layout and production in digital packaging.

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26 Transition of microelectronic pakaging from pin-in-hole to fine-pitch surface mount. 3 mm PQFP 300-500 I/O (chip) Fig. 27 Direct chip attach and multi-chip BGA assembly interaction substrates and for electronic assembly. The IPC (1995) Roadmap report described the printed circuit industry capability and the movement towards high volume dense circuitry processes. 6. 30 shows a broad spectrum of examples of organic packaging assembly: from wirebond, TAB to flip chip, PEM, PBGA, to chip scale packages (CSP), multichip and single chip packages, surface mount and pin-in-hole and rigid printed circuit and flexible circuits.

32. This plane has no usable wiring capacity over the BGA area. 33), two lines per channel of wiring can be reasonably achieved. The authors found that BGA carriers with more than 350 I/Os on a 50 mil grid require six to eight layers just for their own escape, while the SLC would reduce that to two to three layers, resulting in 60% to 80% improvement. 34). 9 Die escapes versus die size. ) Die size (mils) l/Os with std wiring l/Os with fine lines l/Os with std SLC l/Os with fine line SLC 200 400 600 110 272 481 142 336 581 197 261 568 933 444 737 40 Manufacturing challenges in electronic packaging: an overview Fig.

The industry effort to meet the ultra-fine pitch wirebond needs are discussed in recent articles by Leohardt (1996) and by D'Ignazio (1996). 20. The forecasts for the five market segments chip JlO pads and chip sizes for the next 15 years have been published in the 1994 SIA Roadmap. 05{2001} --+-- Commodity ~ ~ 'tJ ftJ Q. 0 :::: . --- Cost/Perform. ~ High Perform. a E 2000 :s Z 1000 o ~~~ o __ - L __ ~ 10 ____ ~ 20 __ ~ __ ~ ____ 30 ~~ 40 Square Chip Size (mm) Fig. 35 Peripheral array chip, JlO capability compared to projected requirements.

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